Active matrix display

ABSTRACT

An active matrix display has a column driver for providing signals to the pixels for driving the display elements, the column driver comprising digital to analogue converter circuitry providing a first number of display element drive levels. Within each pixel, the first number of display element drive levels is converted into a second, greater number, of pixel grey levels. This combines multi-level digital to analogue conversion with in-pixel level generation and enables the complexity of the DACs to be reduced so that they can be integrated onto the display substrate, for example using low temperature polysilicon processing.

The invention relates to an active matrix display, and in particular toan active matrix display in which the pixels are driven to multiple greylevels, using digital to analogue converter circuits.

Active matrix liquid crystal displays (AMLCDs) are one well knownexample of active matrix display. In such displays, an active plate anda passive plate sandwich a liquid crystal. The active plate includes anumber of electrodes for applying electric fields to the liquid crystaland the electrodes are generally arranged in an array. Row and columnelectrodes extending along the rows and columns of pixel electrodesconnect and drive thin film transistors which drive respective pixelelectrodes.

The row and column electrodes are driven to control the thin filmtransistors to control the charge stored on corresponding pixelelectrodes. Each pixel may also include a capacitor for maintainingcharge on the pixel.

One difficulty is in providing the necessary circuits for decodingincoming signals and driving the row and column electrodes. Generally,such driver circuits are arranged around the outside the pixel array.

There is currently much interest in the use of low temperaturepolysilicon (LTPS) to integrate some of the functions of a driver IConto the glass of an AMLCD. Integration helps save some of the IC costand can also make the display more compact. One of the functions whichit is desirable to integrate is the digital to analogue converters(DACs) used to convert digital input data into the analogue voltagerequired to fix the transmission of an LC pixel. The complexity of DACson glass increases significantly as the number bits/pixel is increased.This is because DACs with high conversion accuracies (at least thosewhich can be implemented in LTPS) take up a large area on the glass, andthey may not then be cost competitive with the equivalent DAC on asilicon substrate. This is a problem because video and still imagesrequire 6 bits/pixel if unpleasant visual artefacts, especially visiblein images where colours change very gradually, are to be avoided.

Various driving schemes are also known which drive each pixel with onebit data. This can avoid the need for complicated driver circuits, butof course at the expense of poor image quality. Various techniques arealso known which enable a one bit drive scheme to produce a grey leveloutput from the pixel, albeit with a small number of grey levels. One ofthese techniques is “area weighted grey scaling”. In this approach, apixel is divided into smaller sub-pixel areas, and these may havedifferent areas. For example, two sub-pixels with areas in the ratio 1:2can be driven with one bit data to provide four different lightintensity outputs.

According to the invention there is provided an active matrix display,comprising:

an array of pixels provided over a common substrate, each pixelcomprising a display element and a switching device; and

a column driver for providing signals to the pixels for driving thedisplay elements, the column driver comprising digital to analogueconverter circuitry and providing a first number of display elementdrive levels greater than 2,

wherein each pixel comprises means for converting the first number ofdisplay element drive levels into a second, greater number, of pixelgrey levels.

This arrangement combines multi-level digital to analogue conversionwith in-pixel level generation. This enables the complexity of the DACsto be reduced so that they can be integrated onto the display substrate,for example using low temperature polysilicon processing.

The means for converting may comprise, within each pixel, at least firstand second display elements (i.e. sub-pixels) having different areas. Inthis way, weighted grey scale driving is used within the pixels.

The first and second display elements can then have areas in the ratio1:2. In this case, for any two drive levels, it is possible to generatetwo additional intermediate grey scale levels. Thus, if the two drivelevels are two adjacent levels of the DAC, then two additionalintermediate levels can be generated.

In another embodiment, the means for converting may comprise, withineach pixel, charge redistribution circuit elements. This provides analternative in-pixel level generation. For example, two display elements(sub-pixels) may be used, with an input switch between the input to thepixel and a first display element and a charge redistribution switchbetween the first and second display elements.

With 2 bit in-pixel level generation, as in the two examples above, forproviding 6 bit output (64 levels), 5 bit digital to analogue circuitrycan be used. In fact less than all 32 outputs of the 5 bit DAC arerequired, simplifying the circuitry further.

For example, 22 possible levels are required to implement a 6 bit drivescheme in the area weighting version. In order to convert from the 6 bitdrive signal, a converter can then be provided for deriving a signal forselecting which one (or pair) of the first number of levels to apply toeach display element.

This converter preferably comprises a divider for dividing by 3 andproviding a divisor and a remainder. Thus, a 64 bit signal can bedivided by 3 to provide a divisor between 0 and 21 and a remainder willbe 0,1 or 2.

In the area weighting case, the divisor can thus determine which of thefirst number of levels is applied to one or both of the displayelements, and the remainder determines which one or ones of the displayelements this determined level is applied to.

An adjacent level, for example the next higher level, is then applied tothe display elements (if any) to which the determined level is notapplied. Thus level n is applied to both display elements for a firstbrightness, levels n and n+1 are applied for a second brightness andlevels n+1 and n are applied for a third brightness.

Each pixel may further comprise a memory element for storing digitaldrive values for the display elements of each pixel. For example, theweighted grey scale technique can also be used for a standby mode ofoperation.

The invention also provides a method of driving an active matrixdisplay, comprising:

providing first and second drive voltages to a display pixel havingfirst and second display elements, the first and second drive voltagesbeing selected from two adjacent drive voltage levels of a digital toanalogue converter which has more than 2 analogue output levels; and

within the pixel, generating an intermediate grey level corresponding toa drive voltage between the first and second levels.

This method combines an analogue drive scheme with in-pixel levelgeneration. The first display element may have a first area and thesecond display element may have a second area different to the firstarea, area weighting being then being used to generate the intermediategrey level.

Alternatively, charge sharing between the display elements can be usedto generate the intermediate grey level.

The analogue drive voltages are provided from a column driver circuitwhich may be integrated onto the active plate of the active matrixdisplay, and the complexity of the DAC is reduced by the in-pixelconversion.

In one example, a 5 bit input for the DAC is derived from a 6 bit datasignal by dividing the 6 bit data signal by 3 and providing a divisorand a remainder. The divisor then determines the first drive voltage,and the remainder determines how the sub-pixels are controlled.

For a better understanding of the invention, embodiments will now bedescribed, purely by way of example, with reference to the accompanyingdrawings in which:

FIG. 1 shows a known liquid crystal pixel circuit;

FIG. 2 shows the general components of a liquid crystal display;

FIG. 3 shows a first example of liquid crystal display of the invention;

FIG. 4 shows a second example of pixel for a liquid crystal display ofthe invention;

FIG. 5 shows in greater detail the implementation of the pixel circuitof FIG. 4; and

FIG. 6 shows a third example of liquid crystal display of the invention.

It should be noted that none of the Figures are to scale. Like orcorresponding components are generally given the same reference numeralin different Figures.

FIG. 1 shows a conventional pixel configuration for an active matrixliquid crystal display. The display is arranged as an array of pixels inrows and columns. Each row of pixels shares a common row conductor 10,and each column of pixels shares a common column conductor 12. Eachpixel comprises a thin film transistor 14 and a liquid crystal cell 16arranged in series between the column conductor 12 and a commonelectrode 18. The transistor 14 is switched on and off by a signalprovided on the row conductor 10. The row conductor 10 is thus connectedto the gate 14 a of each transistor 14 of the associated row of pixels.Each pixel additionally comprises a storage capacitor 20 which isconnected at one end 22 to the next row electrode, to the preceding rowelectrode, or to a separate capacitor electrode. This capacitor 20stores a drive voltage so that a signal is maintained across the liquidcrystal cell 16 even after the transistor 14 has been turned off.

In order to drive the liquid crystal cell 16 to a desired voltage toobtain a required grey level, an appropriate analogue signal is providedon the column conductor 12 in synchronism with a row address pulse onthe row conductor 10. This row address pulse turns on the thin filmtransistor 14, thereby allowing the column conductor 12 to charge theliquid crystal cell 16 to the desired voltage, and also to charge thestorage capacitor 20 to the same voltage. At the end of the row addresspulse, the transistor 14 is turned off, and the storage capacitor 20maintains a voltage across the cell 16 when other rows are beingaddressed. The storage capacitor 20 reduces the effect of liquid crystalleakage and reduces the percentage variation in the pixel capacitancecaused by the voltage dependency of the liquid crystal cell capacitance.

The rows are addressed sequentially so that all rows are addressed inone frame period, and refreshed in subsequent frame periods.

As shown in FIG. 2, the row address signals are provided by row drivercircuitry 30, and the pixel drive signals are provided by column addresscircuitry 32, to the array 34 of display pixels. The column addresscircuitry includes digital to analogue converters (DACs) for convertinga digital control signal, for example a 6 bit control signal, into anappropriate analogue level for driving a column conductor 12 associatedwith the DAC.

It is difficult to integrate large DACs, for example 6 bit DACs, ontothe substrate of the pixel array, but this integration is desirable fora number of reasons. The invention is therefore concerned withsimplifying the DAC circuitry whilst maintaining the grey scaleresolution.

A first example of display according to the invention is shown in FIG.3, in which the same reference numerals are used as in FIGS. 1 and 2 forthe same components.

Each pixel comprises (at least) first and second display elements 40,42,namely sub-pixels, having areas in the ratio 1:2 as schematically shownin FIG. 3. This enables weighted grey scale driving to be carried out.Each sub-pixel 40,42 is addressed using a sub-row conductor 10 a,10 b sothat there are twice as many sub-row conductors as rows of pixels. In apreferred example, data of less than 6 bit D/A conversion accuracy isfed onto the sub-pixels, and extra accuracy is created by driving thesub-pixels to different grey levels.

Sub-pixels 40 have associated pixel circuits 44 and sub pixels 42 haveassociated pixel circuits 46. These pixel circuits may be as in FIG. 1,although it will be understood that there are many different specificknown pixel circuit designs. Each sub-pixel also is driven by a sharedcolumn conductor 12. The number of outputs from the column driver 32,and therefore the number of DACs, is thus still equal to the number ofcolumns of full pixels.

Alternatively, separate columns may be provided for each sub-pixel, butthe sub-pixels may share a common row electrode. Although this wouldincrease the complexity of the column drive circuit, it may not be asignificant increase since the voltages applied to the pairs ofsub-pixels are closely related, being adjacent grey scale voltages.

The sub-pixels are driven either to the same grey level or the next greylevel, as follows: Sub-pixel 42 Sub-pixel 44 Effective Pixel Output n nn n + 1 n n + 1/3 n n + 1 n + 2/3

This arrangement combines multi-level digital to analogue conversionwith area weighting grey scale techniques. This enables the complexityof the DACs to be reduced so that they can be integrated onto thedisplay substrate, for example using low temperature polysiliconprocessing.

This specific implementation introduces 2 additional grey levels betweenevery pair or grey levels provided by the DACs. In this case, greylevels n and n+1 are provided by the DACs and grey levels n+⅓ and n+⅔are generated as a result of applying these grey levels to differentsub-pixels. Hence, if the DACs provide m grey levels, the area weightedgrey scale technique generates 2 new levels for every pair of greylevels provided by the DAC. There are m−1 pairs, so 2(m−1) new levelsare generated to be added to the original m grey levels from the DAC,making 3 m−2 grey levels in total. In order to generate a 6 bit image,64 grey levels are needed in total, implying that m=22. If the greylevel voltages from the DAC are equally spaced, all 64 levels will beequally spaced. However, it is more likely that some Gamma correctionwill be generated by the DACs. In this case, the new grey levels arelinear interpolations between each pair of grey levels.

The DACs therefore require 22 voltages to be available for decoding ontothe columns. This is greater than the 16 required for a conventional 4bit DAC, but less than the 32 required for a 5 bit DAC and much lessthan the 64 required for a 6 bit DAC. The DAC is therefore likely to bemuch smaller than a conventional 6 bit DAC. One issue, however, is thedecoding of the 6 bit data signal to select the correct one out of the22 voltages available in the DAC and to order these correctly in time toensure the sub-pixels are set to the correct grey levels. In fact, thiscan be done quite simply.

The 6 bit data 45 fed to the display has values between 0 and 63. Ifthis is fed into a +3 block 46 (either in LTPS or in a separatecontroller IC), two outputs will be generated: the divisor and theremainder. The divisor will lie between 0 and 21, each representing aunique one of the 22 voltages available in the DAC. The remainder willlie between 0 and 2. A 0 remainder requires that both sub-pixels are setto the same grey level, say level n. A 1 remainder requires that thesmaller sub-pixel 42 is set to the adjacent grey level (n+1) whilst thelarger pixel 44 is set to level n. A 2 remainder requires thisassignation to be reversed, so that the smaller sub-pixel 42 is set tothe grey level n whilst the larger pixel 44 is set to level n+1. Theremainder is thus used to control the row address circuitry in theexample of FIG. 3.

In practice, the controller IC would use the remainder to generate asuitable stream of data, with two sets of data per row (one for eachsub-row) in sequence, with the first and second data values set to thecorrect value to select the correct one of the 22 available voltages.Each data set must be 5 bit, as the decoder must select from one of 22available voltages, not just 16 as would be the case for a 4 bit DAC.

In summary, therefore, the DAC of this implementation requires decodersto select one of 22 available voltages using a 5 bit data signal runningat twice the rate (because of the two sub row conductors 10 a, 10 b) ofa display without area-weighted grey levels but which is capable ofachieving 6 bit images.

As the sub-pixels are always driven to adjacent grey levels, the visualartefacts usually associated with area-weighted grey scale techniqueswhen used with a bi-level electro-optic effect will be invisible.Furthermore, the sub-pixels will be driven to near-identical voltages sothe column will already be nearly at the correct voltage when the secondsub-pixel is charged. As a result, in spite of the fact that the displayhas, effectively, twice the normal number of rows, the time required forcharging the second sub-pixel can be very short. This will allow a largefraction of the line time for charging the first sub-pixel so that therequirement on the charging time of the DACs will be little changed fromthat of a display without sub-pixellation. This means that the DAC powerconsumption will only be slightly increased over a display withoutsub-pixellation and just 4 bit DACs. A small store can be provided toeven out the flow of data from the controller IC.

The display can be driven with each sub-row selected separately. In thiscase, the shared column conductor is used for one sub-row in one addressperiod and used for the other sub-row for the other address period.Alternatively, both sub-rows can be selected and charged together, thenone sub-row deselected, a new voltage at an adjacent grey level madeavailable at the DACs and a further short settling time allowed beforemoving on to the next row. In this case, the addressing of the secondsub-row is only required to change the charge on the sub-pixel by anamount corresponding to at most one grey level (if at all), so that thesecond row address pulse can be shorter than the combined row addresspulse.

An especially attractive feature of this implementation is theuncomplicated way in which the use of this area-weighted grey scaletechniques fits together with a way of improving an unrelated, butequally important, factor in the design of displays for mobileelectronic products, namely the display power consumption. LTPS can beused to reduce the power consumption of an AMLCD in a mode known asstandby mode through the use of a memory element integrated in eachpixel.

The example above combines sub-pixel area weighting with low resolutionanalogue drive to increase the grey scale resolution. There are,however, alternative in-pixel arrangements which can be used to provideadditional voltage levels within the pixels.

U.S. Pat. No. 5,448,258 discloses a display in which in-pixel DACcircuitry is used to enable the pixels to be driven with digitalsignals, by addressing each pixel with a sequence of data inputsrepresenting the bits of the digital drive word. Within each pixel, acharge redistribution technique is used to generate the correspondinganalogue drive voltage. Although this technique is used in U.S. Pat. No.5,448,258 to allow multi-bit digital addressing of the pixels, the samecharge redistribution technique can be employed as an alternative methodof providing additional drive levels within the pixel, and this documentis incorporated herein as reference material.

FIG. 4 shows the pixel arrangement of U.S. Pat. No. 5,448,258. Thedisplay element of each pixel is divided into two sub-pixels 16 a, 16 b,which act as capacitors for the charge sharing function. Switches S1 andS2 control the application of the column drive voltage to the pixel aswell as the charge sharing operation, whereas switch S3 is for a restoperation. The input switch S1 is between the input and the pixelelectrode for one sub-pixel 16 a, and the charge redistribution switchS2 is between the pixel electrodes of the two sub-pixels 16 a, 16 b. Thetwo display sub-pixels are thus in parallel with a shared commonelectrode. The reset switch S3 is provided to enable discharge of thedisplay sub-pixel 16 b.

To perform a conversion, switch S3 is first closed to dischargesub-pixel 16 b and to set the voltage at point V2 to zero. There thenfollow a number of cycles during which the switches S1 and S2 areoperated. During each cycle, a voltage at the input, Vi(n), is appliedto the input of the circuit.

In the use of the circuit in U.S. Pat. No. 5,448,258, this voltage takesone of two values and represents the state of each bit in turn of thedigital data to be converted. In this application, the same circuit canbe used to define intermediate grey levels from two adjacent analogueinput levels, with a different switching operation, which will now bedescribed.

The lower analogue voltage level is first stored on both sub-pixels 16a, 16 b. A 2 bit digital to analogue conversion is then carried outusing the two analogue levels as the voltage levels representing digital“0” and “1”.

Two bits of data are presented to the circuit in series, each bitcomprising either the analogue value representing “1” or the analoguevalue representing “0”. During each cycle, the switch S1 is first closedallowing the sub-pixel 16 a to charge to the input voltage level. SwitchS1 is then opened and switch S2 closed allowing charge sharing to takeplace between the two sub-pixels. The voltages V1 and V2 equalise and S2is then opened once more to complete the cycle. Thus, the same voltageis eventually stored on both sub-pixels, which improves image quality.

The number of cycles determines the resolution, i.e. the number of bits,of the conversion. Thus, there are two cycles for the two bit conversiondescribed above. At the end of the conversion the voltages V1 and V2have a value which lies between the two adjacent analogue voltage levels(or is equal to the lower analogue level if the digital word is 00). Thesequence of digital input bits is effectively scaled by increasingpowers of two and the final voltage therefore represents the analogueequivalent of the digital data fed into the circuit.

In this conversion, three additional voltage levels result between eachpair of analogue voltage levels, so that 4 m−3 levels result from manalogue levels, using the same logic as above. 17 analogue levels arethus needed, which again requires DAC circuits of complexity between 4and 5 bits.

FIG. 5 shows an implementation of the pixel of FIG. 4. As shown, theswitches S1 and S2 are implemented as TFTs, and the capacitors aredefined by the LC cells themselves. It is seen that the picture pixel ofFIG. 5 contains all the elements of the converter circuit of FIG. 4except the discharging switch S3. However the voltage on the sub-pixel16 b can still be discharged, or reset, simply by holding the columnvoltage at an appropriate level and simultaneously turning on both TFTS1 and TFT S2. As shown, there are two row conductors 10 a, 10 b, butthe second row conductor may be the single row conductor for the nextrow with appropriate design of the row control voltages.

In this pixel circuit, the sub-pixels may be of equal size, althoughthey may also be different sizes (and therefore capacitances). Thisdesign provides an alternative way of converting a first number ofanalogue display drive levels into a second, greater number, of pixelgrey levels.

It has been proposed to integrate memory storage elements into thestructure of display devices for this purpose. It has also beenrecognised that the introduction of memory cells does not necessarilyrequire an increase in the size or complexity of the device substrate.For example, in a liquid crystal display, the pixel electrode (forexample 40 and 42 in FIG. 3) occupies a significantly greater area thanthe drive transistor and storage capacitor (44 and 46 in FIG. 3). If thepixel electrode is able to overlie the electronic components, it ispossible to introduce additional components such as memory elementsadjacent the drive transistors, without changing the size of the pixelelectrodes.

Various different structures have been proposed for the active plate ofactive matrix liquid crystal displays, in which memory elements areassociated with the display pixels. In each case, the purpose of thememory element is to store the pixel data, so that the pixels can bedriven from integrated memory elements as well as from applied signaldata.

A major benefit of this possibility is that a reduction in powerconsumption can be achieved. In particular, one problem withconventional displays arises from the need to invert the liquid crystaldriving voltages, typically each frame. As a consequence of the 60 Hzframe rate, alternating the polarity gives rise to a 30 Hz signal, whichproduces flicker. To reduce this flicker, it is known to invert thepolarity of the pixel drive signals for adjacent rows of pixels.However, this results in a high power consumption drive scheme.

A memory element associated with each pixel can be used to enable areduction in power consumption, by avoiding the need to rewrite data toeach pixel when the pixel data is unchanged. In addition, the pixels canbe driven in two modes—one in which signal data is applied to the pixel,and one in which memory data is applied to the pixel.

In the standby mode, a fixed image at low colour depth (e.g. just 1-2bits/pixel) can be used to convey a simple status message to the user.Using LTPS to create an in-pixel memory of 1-2 bits allows the driver ICand interface to be powered down in this standby mode, thereby savingpower. The in-pixel memory fixes selected sub-pixels black or whitedepending on the desired grey level and the eye is relied upon tointegrate the combined effect of these sub-pixels into an average greylevel. Unfortunately, the eye can usually resolve this sub-pixellation,as the difference in grey level between the sub-pixels is large, beingeither black or white. As a result, quite unpleasant visual artefactscan be seen, again most visible in images with gradually changingcolours.

In the area weighting arrangement described above, the similarity ofgrey level to which the two sub-pixels are set in the normal drive modeOust one grey level apart) will ensure that the visual artefacts notedabove for the area-weighted grey scale technique do not apply. Inaddition, the additional power consumption in the DACs is not as greatas might be implied by the need to drive a display with twice as manyrows.

FIG. 6 shows a modification to FIG. 3 to include memory capability.Within the area 50 of each pixel (which is the combined area of the twosub-pixels 40,42), there are provided two memory cells 52 (shown hatchedin FIG. 4). Memory address circuitry 54, 56 is provided to enable datato be written to each memory cell, and to enable data to be read fromeach memory cell. This can be carried out independently of the signaldata associated with each pixel, or else the memory cells may be ableonly to output their data to the sub-pixels. Each memory cell 52 isassociated with a unique pair of row and column memory address lines 58,60.

In the example of FIG. 6, the memory cells 52 are associated withseparate memory address circuitry 54, 56. Furthermore, separate row andcolumn address lines 58, 60 are provided for the memory cells 52.However, it is equally possible for the pixel row or column addresslines 10, 12 to be shared between the pixel circuit and the memory cells22. This will depend on the functionality to be implemented. This willbe apparent to those skilled in the art.

This arrangement provides a way of making a display with 2 bits/pixelstandby images and 6 bit/pixel video images using a DAC of complexityintermediate between and 4 and a 5 bit DAC. The technique could be usedto add extra colour depth to an amorphous silicon display, as well asenabling of DACs for a LTPS display.

The integration of memory elements into a pixel design using chargeredistribution instead of area weighting is also possible, but will notbe described in detail in this application.

In the example above, two different possible ways of increasing thenumber of analogue levels within each pixel have been disclosed. Otherin-pixel level generation techniques may also be possible, as will beapparent to those skilled in the art.

In the examples above, the display is a liquid crystal display. Itshould be understood that the invention can be applied to other types ofdisplay, such as electroluminescent displays. Also, the specificexamples combine a two bit pixel with a DAC of 4-5 bit complexity toachieve 6 bit resolution. Other examples are of course possible, and theinvention more generally takes advantage of in pixel level generation,for example based on sub-pixellation or charge redistribution, to enablea reduction in DAC complexity to achieve a given resolution.

Other examples will be apparent to those skilled in the art.

1. An active matrix display, comprising: an array of pixels providedover a common substrate, each pixel comprising a display element and aswitching device; and a column driver for providing signals to thepixels for driving the display elements, the column driver comprisingdigital to analogue converter circuitry and providing a first number ofdisplay element drive levels greater than 2, wherein each pixelcomprises means for converting the first number of display element drivelevels into a second, greater number, of pixel grey levels.
 2. A displayas claimed in claim 1, wherein the means for converting comprises,within each pixel, at least first and second display elements havingdifferent areas.
 3. A display as claimed in claim 2, wherein the firstand second display elements have areas in the ratio 1:2.
 4. A display asclaimed in claim 1, wherein the means for converting comprises, withineach pixel, charge redistribution circuit elements.
 5. A display asclaimed in claim 4, wherein the charge redistribution elements comprisetwo display elements, an input switch between the input to the pixel anda first display element and a charge redistribution switch between thefirst and second display elements.
 6. A display as claimed in claim 1,wherein the digital to analogue circuitry receives a 5 bit digital word.7. A display as claimed in claim 6, wherein the output of the digital toanalogue circuitry comprises a number of levels less than
 32. 8. Adisplay as claimed in claim 7, wherein the output digital to analoguecircuitry comprises 22 possible levels.
 9. A display as claimed in claim1 further comprising a converter for deriving from a 6 bit drive signala signal for selecting which one or ones of the first number of levelsto apply to each display element.
 10. A display as claimed in claim 9,wherein the converter comprises a divider for dividing by 3 andproviding a divisor and a remainder.
 11. A display as claimed in claim2, wherein the divisor determines which of the first number of levels isapplied to one or both of the display elements, and the remainderdetermines which one or ones of the display elements this determinedlevel is applied to.
 12. A display as claimed in claim 11, wherein anadjacent level is applied to the display elements (if any) to which thedetermined level is not applied.
 13. A display as claimed in claim 1,comprising a plurality of row conductors, a number of row conductorsbeing associated with each row of pixels corresponding to the number ofdisplay elements within each pixel.
 14. A display as claimed in claim 1,wherein each pixel comprises a memory element for storing digital drivevalues for the display elements of each pixel.
 15. A display as claimedin claim 1, wherein the digital to analogue circuitry is provided on thecommon substrate.
 16. A display as claimed in claim 15, wherein thepixel array and the digital to analogue circuitry are formed using lowtemperature polysilicon processing.
 17. A method of driving an activematrix display, comprising: providing first and second drive voltages toa display pixel having first and second display elements, the first andsecond drive voltages being selected from two adjacent drive voltagelevels of a digital to analogue converter which has more than 2 outputlevels; and within the pixel, generating an intermediate grey levelcorresponding to a drive voltage between the first and second levels.18. A method as claimed in claim 17, wherein the first display elementhas a first area and the second display element has a second areadifferent to the first area, area weighting being used to generate theintermediate grey level.
 19. A method as claimed in claim 18, whereinthe first and second drive voltages are provided by a digital toanalogue converter which receives a 5 bit input derived from a 6 bitdata signal by dividing the 6 bit data signal by 3 and providing adivisor and a remainder.
 20. A method as claimed in claim 19, whereinthe divisor determines the first drive voltage, and the remainderdetermines whether the first and second drive voltages are the same orare different.
 21. A method as claimed in any one of claim 18, wherein aplurality of sub-rows of pixels are addressed in turn, each sub-rowcomprising respective display elements for each pixel.
 22. A method asclaimed in any one of claim 18, wherein a plurality of rows of pixelsare addressed in turn, each row being addressed once to address bothdisplay elements and a second time to readdress the second displayelement.
 23. A method as claimed in claim 17, wherein charge sharingbetween the display elements is used to generate the intermediate greylevel.
 24. A method as claimed in claim 23, wherein the first and seconddrive voltages are provided by a digital to analogue converter whichreceives a 5 bit input.
 25. A method as claimed in any one of claims 17to 24, wherein the drive voltages are provided from a column drivercircuit integrated onto the active plate of the active matrix display.